MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 226

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

External Interface Module (EIM)
13.3
The device uses its system clock to generate CLKOUT. Therefore, the external bus operates at the same
speed as the bus clock rate, where all bus operations are synchronous to the rising edge of CLKOUT, and
some of the bus control signals (BS, OE, and CSn,) are synchronous to the falling edge, shown in
Figure
13.4
Data transfers between the processor and other devices involve the following signals:
The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT. Read data
is latched into the processor on the rising edge of CLKOUT.
The bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit
data ports. Aspects of the transfer, such as the port size, the number of wait states for the external slave
being accessed, and whether internal transfer termination is enabled, can be programmed in the chip-select
control registers (CSCRs) and the DRAM control registers (DACRs).
Figure 13-2
if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to
D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with the MSB and going
to the LSB.
13-2
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Falling-Edge
Rising-Edge
13-1. Bus characteristics may differ somewhat for interfacing with external DRAM.
Address bus (A[23:0])
Data bus (D[31:0])
Control signals (TS and TA)
CSn, OE, BS
Attribute signals (R/W, SIZ, and TIP)
CLKOUT
Bus Characteristics
Data Transfer Operation
Signals
Signals
Inputs
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shows the byte lanes that external memory should be connected to and the sequential transfers
= Required input setup time relative to CLKOUT edge
= Required input hold time relative to CLKOUT edge
= Propagation delay of signal relative to CLKOUT edge
= Output hold time relative to CLKOUT edge
Figure 13-1. Signal Relationship to CLKOUT for Non-DRAM Access
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
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Freescale Semiconductor
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