MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 121

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.3.4.2
The CFMCLKD is used to set the frequency of the clock used for timed events in program and erase
algorithms.
All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once.
Freescale Semiconductor
Bits
4–0
Bits
5–0
7
6
5
7
6
CFM Clock Divider Register (CFMCLKD)
Address
Reset
Field
R/W
PRDIV8
DIVLD
Name
KEYACC
DIV
CBEIE
Name
CCIE
DIVLD
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
—
R
7
Figure 6-5. CFM Clock Divider Register (CFMCLKD)
Clock divider loaded
1 CFMCLKD has been written since the last reset.
0 CFMCLKD has not been written.
Enable prescaler divide by 8
1 Enables a prescaler that divides the CFM clock by 8 before it enters the
0 The CFM clock is fed directly into the CFMCLKD divider.
Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the
CFM input clock down to a frequency between 150 kHz and 200 kHz. The
frequency range of the CFM clock is 150 kHz to 102.4 MHz.
Table 6-5. CFMCLKD Field Descriptions
PRDIV8
CFMCLKD divider.
Table 6-4. CFMCR Field Descriptions
Command buffer empty interrupt enable. The CBEIE bit is readable and writable.
CBEIE enables an interrupt request when the command buffer for the Flash
physical blocks is empty.
1 Request an interrupt whenever the CBEIF flag is set.
0 Command buffer empty interrupts disabled
Command complete interrupt enable. The CCIE bit is readable and writable.
CCIE enables an interrupt when the command executing for the Flash is
complete.
1 Request an interrupt whenever the CCIF flag is set.
0 Command complete interrupts disabled
Enable security key writing. The KEYACC bit is readable and only writable if the
KEYEN bit in the CFMSEC register is set.
1 Writes to the Flash array are interpreted as keys to open the back door.
0 Writes to the Flash array are interpreted as the start of a program, erase, or
Reserved, should be cleared.
verify sequence.
6
5
IPSBAR + 0x1D_0002
0000_0000
Description
R/W
Description
DIV
ColdFire Flash Module (CFM)
0
6-9