MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 384
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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General Purpose Timer Modules (GPTA and GPTB)
20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
20.5.18 GPT Port Data Register (GPTPORT)
20-16
Bit(s)
Bit(s)
15–0
7–4
3–0
Address
Reset
Field
R/W
Address
Reset
Field
R/W
PORTT
PACNT
15
Name
Name
—
Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
7
Figure 20-20. GPT Port Data Register (GPTPORT)
Contains the number of active input edges on the PAI pin since the last reset.
Note: Reading the pulse accumulator counter registers immediately after an active
edge on the PAI pin may miss the last count since the input first has to be synchronized
with the bus clock.
To ensure coherent reading of the PA counter, such that the counter does not
increment between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime.
Reserved, should be cleared.
GPT port input capture/output compare data. Data written to GPTPORT is buffered
and drives the pins only when they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1)
reads the latched value. Writing to a pin configured as a GPT output does not change
the pin state. These bits are read anytime (read pin state when corresponding
PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write
anytime.
Table 20-20. GPTPACR Field Descriptions
Table 20-21. GPTPORT Field Descriptions
6
—
IPSBAR + 0x1A_001A, 0x1B_001B
IPSBAR + 0x1A_001D, 0x1B_001D
5
0000_0000_0000_0000
0000_0000
4
PACNT
R/W
R/W
Description
3
Description
PORTT
Freescale Semiconductor
0
0
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