MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 211

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.4
This subsection describes the memory map and register structure.
11.4.1
Refer to
base address of 0x0013_0000.
11.4.2
The EPORT programming model consists of these registers:
11.4.2.1 EPORT Pin Assignment Register (EPPAR)
Freescale Semiconductor
Address
•
•
•
•
•
•
1
2
0x0013_0000
0x0013_0002 EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER)
0x0013_0004
0x0013_0006
Reset
Field
R/W
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
Writing to reserved address locations has no effect, and reading returns 0s.
IPSBAR
The EPORT pin assignment register (EPPAR) controls the function of each pin individually.
The EPORT data direction register (EPDDR) controls the direction of each one of the pins
individually.
The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.
The EPORT data register (EPDR) holds the data to be driven to the pins.
The EPORT pin data register (EPPDR) reflects the current state of the pins.
The EPORT flag register (EPFR) individually latches EPORT edge events.
Offset
Table 11-2
Memory Map and Registers
Memory Map
Registers
15
EPPA7
14
for a description of the EPORT memory map. The EPORT has an IPSBAR offset for
EPORT Data Register (EPDR)
EPORT Flag Register (EPFR)
13
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
EPPA6
Figure 11-2. EPORT Pin Assignment Register (EPPAR)
12
Bits 15–8
Table 11-2. Edge Port Module Memory Map
EPORT Pin Assignment Register (EPPAR)
11
EPPA5
IPSBAR + 0x0013_0000, 0x0013_0001
10
0000_0000_0000_0000
9
R/W
EPPA4
8
EPORT Pin Data Register (EPPDR)
7
EPPA3
Reserved
Bits 7–0
6
5
EPPA2
2
4
Edge Port Module (EPORT)
EPPA1
3
2
Access
S/U
S/U
S
S
1
—
R
1
0
11-3