MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 516
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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General Purpose I/O Module
26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)
The PBCDPAR controls the pin function of ports B, C, and D.
The PBCDPAR register is read/write.
26-16
1
Address
Reset state determined during reset configuration as shown in
Reset See Note 1
R/W:
Field
Bits
5–0
7
6
PBPA
R/W
7
1
Figure 26-19. Port B/C/D Pin Assignment Register (PBCDPAR)
Single chip mode
Note if the port size of the external boot device is less than the port size
of the external SDRAM, the PBCDPAR register must be written after reset
to enable the primary function(s) on ports B,C, and D, before any SDRAM
accesses are attempted.
1
Master mode
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Operation
See Note 1
Mode of
PCDPA
PCDPA
Name
PBPA
R/W
—
6
Table 26-8. Reset Values for PBCDPAR Bits
Table 26-7. PBCDPAR Field Descriptions
Port B pin assignment. Configures the port B pins for their primary
function (D[23:16]) or digital I/O.
1 Port B pins configured for primary function (D[23:16])
0 Port B pins configured for digital I/O
Ports C,D pin assignment. Configures the port C and D pins for their
primary functions (D[15:8], D[7:0]) or digital I/O.
1 Port C,D pins configured for primary function (D[15:8], D[7:0])
0 Port C,D pins configured for digital I/O
Reserved, should be cleared.
External Boot
Port Size of
5
Device
16-bit
32-bit
8-bit
N/A
IPSBAR + 0x10_0050
1
PBPA Reset
Value
0
1
1
0
Table
Description
00_0000
26-8.
—
R
PCDPA Reset
Value
0
0
1
0
Freescale Semiconductor
0
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