MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 193

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source
1–7 (from the Edgeport module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum
of 8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt
source is hardwired to the given level, and represents the mid-point of the priority within the level. For the
fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in
the 8-bit interrupt control register (ICRnx).
The operation of the interrupt controller can be broadly partitioned into three activities:
10.1.1.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register to
determine if there are active requests. This is the recognition phase.
Freescale Semiconductor
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Recognition
Prioritization
Vector Determination during IACK
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 10-1. Interrupt Priority Scheme (continued)
Interrupt
ICR[IL]
Level
6
5
4
3
2
1
— (Mid-point)
— (Mid-point)
— (Mid-point)
— (Mid-point)
— (Mid-point)
— (Mid-point)
Priority
ICR[IP]
7–4
3–0
7–4
3–0
7–4
3–0
7–4
3–0
7–4
3–0
7–4
3–0
Supported Interrupt
#6 (IRQ6)
#5 (IRQ5)
#4 (IRQ4)
#3 (IRQ3)
#2 (IRQ2)
#1 (IRQ1)
Sources
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
#8–63
Interrupt Controller Modules
10-3