MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 387

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow
interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
20.6.6
Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the
PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high
levels to enable the divide-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt
enable bit, PAI, enables the PAIF flag to generate interrupt requests.
The PA counter register, GPTPACNT, reflects the number of pulses from the divide-by-64 clock since the
last reset.
20.6.7
An I/O pin used by the timer defaults to general-purpose I/O unless an internal function which uses that
pin is enabled.
The PORTTn pins can be configured for either an input capture function or an output compare function.
The IOSn bits in the GPT IC/OC select register configure the PORTTn pins as either input capture or
output compare pins.
Freescale Semiconductor
Gated Time Accumulation Mode
General-Purpose I/O Ports
The PA can operate in event counter mode even when the GPT enable bit,
GPTEN, is clear.
The PAI input and GPT channel 3 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 3 output mode
and output level bits, OM3 and OL3. Also clear the channel 3 output
compare mask bit, OC3M3.
The GPT prescaler generates the divide-by-64 clock. If the timer is not
active, there is no divide-by-64 clock.
Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
CHANNEL 3 OUTPUT COMPARE
OM3
OL3
ACCUMULATOR
PULSE
OC3M3
NOTE
NOTE
NOTE
PAD
General Purpose Timer Modules (GPTA and GPTB)
20-19