MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 285

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.2.3.2 SDRAM Byte Strobe Connections
Figure 15-5
15.2.3.3 Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To
interface one 2M x 32-bit x 4 bank SDRAM component (8 columns), use the connections shown in
Table
15.2.3.4 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS is issued, the
SDRAM accepts a new address and asserts SCAS every CLKOUT for as long as accesses occur in that
page. In burst page mode, there are multiple read or write operations for every
SDRAM if the requested transfer size exceeds the port size of the associated SDRAM. The primary cycle
of the transfer generates the
or
next access.
Freescale Semiconductor
WRITE
SDRAM Pins
Processor Pins A15
15-24.
commands. As soon as the transfer completes, the
Table 15-23. Processor to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
shows SDRAM connections for port sizes of 32, 16, or 8 bits.
Processor
Pins
Row
Column
SDRAM
Pins
A0
Figure 15-5. Connections for External Memory Port Sizes
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
A14
A1
A15
Byte Enable
A0
15
2
32-Bit Port
16-Bit Port
ACTV
Processor
Data Bus
8-Bit Port
External
Memory
Memory
Memory
Table 15-24. SDRAM Hardware Connections
A13
A2
A14
14
A1
3
and
A12
A3
A13
READ
A2
13
4
A11
D[31:24]
A4
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BS3
A12
A3
12
or
5
A10
A5
WRITE
A11
A4
11
D[23:16]
6
Byte 1
Byte 1
Byte 3
A6
A9
BS2
commands; secondary cycles generate only
A10
indeterminate values
A5
10
7
A17
A7
Driven with
PALL
indeterminate values
D[15:8]
Byte 2
BS1
A9
A6
9
8
A18
A8
Driven with
command is generated to prepare for the
A17
A7
17
16
A19
A9
Byte 3
D[7:0]
BS0
A19
A8
19
18
Synchronous DRAM Controller Module
A10 = CMD
A20
A21
A9
21
20
ACTV
A23
A10
23
22
command in the
BA0
A21
BA1
A22
READ
15-13