MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 593
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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During initial sample, a buffered version of the selected input channel is connected to the sample capacitor
at the input of the sample buffer amplifier.
During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges
the sample capacitor directly. Each CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles.
When an analog-to-digital conversion is complete, the result is written to the corresponding location in the
result word table. The QADC continues to sequentially execute each CCW in the queue until the end of
the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC stops execution of the queue until a new trigger
event occurs. The pause status flag bit is set, and an interrupt may optionally be requested. After the trigger
event occurs, the paused state ends, and the QADC continues to execute each CCW in the queue until
another pause is encountered or the end of the queue is detected.
An end-of-queue condition occurs when:
When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an
interrupt is requested. These situations prematurely terminate queue execution:
28.8.11 Result Word Table
The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is written by the
QADC after completing an analog conversion specified by the corresponding CCW table entry. The result
word table can be read or written, but in normal operation is only read to obtain analog conversions from
the QADC. Unimplemented bits read as 0s and writes have no effect.
Freescale Semiconductor
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Resolution
The CCW channel field is programmed with 63 to specify the end of the queue.
The end-of-queue 1 is implied by the beginning of queue 2, which is specified by the BQ2 field in
QACR2.
The physical end of the queue RAM space defines the end of either queue.
Queue 1 is higher in priority than queue 2. When a trigger event occurs on queue 1 during queue 2
execution, the execution of queue 2 is suspended by aborting the execution of the CCW in progress,
and queue 1 execution begins. When queue 1 execution is complete, queue 2 conversions restart
with the first CCW entry in queue 2 or the first CCW of the queue 2 subqueue being executed when
queue 2 was suspended. Alternately, conversions can restart with the aborted queue 2 CCW entry.
The RESUME bit in QACR2 selects where queue 2 begins after suspension. By choosing to
re-execute all of the suspended queue 2 CCWs (RESUME = 0), all of the samples are guaranteed
to have been taken during the same scan pass. However, a high trigger event rate for queue 1 can
prevent completion of queue 2. If this occurs, execution of queue 2 can begin with the aborted
CCW entry (RESUME = 1).
Any conversion in progress for a queue is aborted when that queue’s operating mode is changed to
disabled. Putting a queue into the disabled mode does not power down the converter.
Changing a queue’s operating mode to another valid mode aborts any conversion in progress. The
queue restarts at its beginning once an appropriate trigger event occurs.
For low-power operation, the stop bit can be set to prepare the module for a loss of clocks. The
QADC aborts any conversion in progress when stop mode is entered.
When the QADC debug bit is set and the CPU enters background debug mode, the QADC freezes
at the end of the conversion in progress. After leaving debug mode, the QADC resumes queue
execution beginning with the next CCW entry. Refer to
information.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 28.3.1, “Debug
Queued Analog-to-Digital Converter (QADC)
Mode” for more
28-55
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