MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 463
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.3.4
The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in
Figure
remains stable low during the high period of the clock pulse.
If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master can then
generate a STOP signal to abort data transfer or generate a START signal (repeated start, shown in
Figure 24-10
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means
end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or START signal
(Figure
24.3.5
The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is
defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (see F in
The master can generate a STOP even if the slave has generated an acknowledgment, at which point the
slave must release the bus. The master may also generate a START signal following a calling address,
without first generating a STOP signal. Refer to
24.3.6
A repeated START signal is a START signal generated without first generating a STOP signal to terminate
the communication, as shown in
another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
Freescale Semiconductor
24-9. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it
24-9).
I2C_SDA by Transmitter
Acknowledge
STOP Signal
Repeated START
I2C_SDA by Receiver
and discussed in
I2C_SCL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 24.3.6, “Repeated
Figure 24-9. Acknowledgement by Receiver
START Signal
Figure
24-10. The master uses a repeated START to communicate with
Bit7
1
Bit6
2
Section 24.3.6, “Repeated START.”
Bit5
3
Bit4
START”) to start a new calling sequence.
4
Bit3
5
Bit2
6
Bit1
7
R/W
Bit0
8
ACK
9
Figure
I
2
C Interface
24-7).
24-9
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