MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 300
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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DMA Controller Module
16.3
The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers
to a fast method of moving data within system memory (including memory and peripheral devices) with
minimal processor intervention, greatly improving overall system performance. The DMA module
consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply
to any of the channels. It is not possible to implicitly address all four channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA
timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus
bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see
Section 16.5.1, “Transfer Requests (Cycle-Steal and Continuous
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits.
Any operation involving the DMA module follows the same three steps:
16.4
This section describes each internal register and its bit assignment. Note that modifying DMA control
registers during a DMA transfer can result in undefined operation.
controller registers. Note the differences for the byte count registers depending on the value of
MPARK[BCR24BIT]. See
16-4
•
1. Channel initialization—Channel registers are loaded with control information, address pointers,
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing and bus
3. Channel termination—Occurs after the operation is finished, either successfully or due to an error.
Dual-address transfers—A dual-address transfer consists of a read followed by a write and is
initiated by an internal request using the START bit or by asserting DREQ. Two types of transfer
can occur: a read from a source device or a write to a destination device. See
information.
and a byte-transfer count.
control for the transfers.
The channel indicates the operation status in the channel’s DSR, described in
“DMA Status Registers
DMA Transfer Overview
DMA Controller Module Programming Model
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 8.5.3, “Bus Master Park Register
(DSR0–DSR3).”
DMA
DMA
Figure 16-3. Dual-Address Transfer
Control and Data
Control and Data
Peripheral
Peripheral
Memory/
Memory/
Modes).”
Table 16-2
(MPARK)” for further information.
shows the mapping of DMA
Figure 16-3
Freescale Semiconductor
Section 16.4.5,
for more
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