MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 457
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.2
The below table lists the configuration registers used in the I
24.2.1
I2ADR holds the address the I
bus during the address transfer when the module is performing a master transfer.
24.2.2
The I2FDR, shown in
bit-rate selection.
Freescale Semiconductor
0x00_030C
0x00_0300
0x00_0304
0x00_0308
0x00_0310
Field
ADR
7–1
IPSBAR
Offset
0
IPSBAR
Offset:
Reset:
Slave address. Contains the specific slave address to be used by the I
for an address match on the bus.
Reserved, must be cleared.
Memory Map/Register Definition
W
R
I
I
0x00_0300 (I2ADR)
2
2
I
I
I
I
I
C Address Register (I2ADR)
C Frequency Divider Register (I2FDR)
2
2
2
2
2
C Address Register (I2ADR)
C Frequency Divider Register (I2FDR)
C Control Register (I2CR)
C Status Register (I2SR)
C Data I/O Register (I2DR)
0
7
Figure
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
6
0
24-3, provides a programmable prescaler to configure the I
2
C responds to when addressed as a slave. It is not the address sent on the
Figure 24-2. I
Table 24-2. I2ADR Field Descriptions
Table 24-1. I
Register
0
5
2
C Address Register (I2ADR)
2
C Module Memory Map
ADR
0
4
Description
2
C interface.
0
3
2
C module. Slave mode is the default I
Access Reset Value
R/W
R/W
R/W
R/W
R/W
0
2
Access: User read/write
0x00
0x00
0x81
0x00
0x00
0
1
2
C clock for
Section/Page
24.2.1/24-3
24.2.2/24-3
24.2.3/24-4
24.2.4/24-5
24.2.5/24-6
I
2
0
0
0
C Interface
2
C mode
24-3
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