MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 419

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the
service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during
servicing can be prevented by clearing QIR[SPIFE].
There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting
QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may
abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it
reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes
the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.
22.5
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 5 MHz. The
QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.
Freescale Semiconductor
1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock
2. Write QDLYR with the desired delays.
3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts.
4. Write QAR with 0x0020 to select the first command RAM entry.
5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00,
6. Write QAR with 0x0000 to select the first transmit RAM entry.
7. Write QDR with sixteen 12-bit words of data.
8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.
9. Set QDLYR[SPE] to enable the transfers.
10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.
11. Write QAR with 0x0010 to select the first receive RAM entry.
12. Read QDR to get the received data for each transfer.
13. Repeat steps 5 through 13 to do another transfer.
edge, and a QSPI_CLK frequency of 5 MHz (assuming a 80-MHz internal bus clock).
0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each
chip select. The chip selects are active low in this example.
Initialization/Application Information
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Queued Serial Peripheral Interface (QSPI)
22-15