HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 8

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Section 6
6.1
6.2
6.3
6.4
ii
Overview............................................................................................................................ 45
5.1.1
5.1.2
5.1.3
Resets................................................................................................................................. 49
5.2.1
5.2.2
Address Errors ................................................................................................................... 50
5.3.1
Interrupts............................................................................................................................ 51
5.4.1
5.4.2
Exceptions Triggered by Instructions................................................................................ 52
5.5.1
5.5.2
5.5.3
When Exception Sources Are Not Accepted..................................................................... 54
5.6.1
5.6.2
Stack Status after Exception Processing Ends................................................................... 55
Notes on Use...................................................................................................................... 56
5.8.1
5.8.2
5.8.3
Overview............................................................................................................................ 57
6.1.1
6.1.2
6.1.3
6.1.4
Interrupt Sources................................................................................................................ 60
6.2.1
6.2.2
6.2.3
6.2.4
Description of Registers .................................................................................................... 64
6.3.1
6.3.2
6.3.3
Interrupt Operation ............................................................................................................ 68
6.4.1
Exception Processing
Types of Exception Processing and Priority ........................................................ 45
Exception Processing Operations ......................................................................... 46
Exception Processing Vector Table...................................................................... 47
Reset ..................................................................................................................... 49
Power-On Reset.................................................................................................... 49
Address Error Exception Processing.................................................................... 50
Interrupt Priority Level......................................................................................... 51
Interrupt Exception Processing ............................................................................ 52
Trap Instructions .................................................................................................. 53
Illegal Slot Instructions ........................................................................................ 53
General Illegal Instructions .................................................................................. 53
Immediately after a Delayed Branch Instruction.................................................. 54
Immediately after an Interrupt-Disabled Instruction............................................ 54
Value of Stack Pointer (SP).................................................................................. 56
Value of Vector Base Register (VBR) ................................................................. 56
Address Errors Caused by Stacking of Address Error Exception Processing...... 56
Interrupt Controller (INTC)
Features ................................................................................................................ 57
Block Diagram...................................................................................................... 58
Pin Configuration ................................................................................................. 59
Register Configuration ......................................................................................... 59
NMI Interrupts...................................................................................................... 60
IRQ Interrupts ...................................................................................................... 60
On-Chip Peripheral Module Interrupts ................................................................ 61
Interrupt Exception Vectors and Priority Rankings ............................................. 61
Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 64
Interrupt Control Register (ICR) .......................................................................... 65
IRQ Status Register (ISR) .................................................................................... 66
Interrupt Sequence................................................................................................ 68
.................................................................................... 45
......................................................................... 57