HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 232

MPU 5V 0K 100-QFP

HD6417011VX20V

Manufacturer Part Number
HD6417011VX20V
Description
MPU 5V 0K 100-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7010r
Datasheet

Specifications of HD6417011VX20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
POR, PWM
Number Of I /o
11
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417011VX20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 12.5.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 12.9 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the
numbers in the flowchart):
1. SCI status check and transmit data write: Read the serial status register (SSR), check that the
2. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
222
Figure 12.8 Communication Among Processors Using Multiprocessor Format (Sending
Serial
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
reads 1); if so, write data in TDR, then clear TDRE to 0.
MPB: Multiprocessor bit
data
Transmitting
processor A
processor
Receiving
(ID = 01)
receiving processor address
ID-transmit cycle:
Data H'AA to Receiving Processor A)
H'01
processor B
Receiving
(MPB = 1)
(ID = 02)
Serial communication line
processor specified by ID
data sent to receiving
Data-transmit cycle:
processor C
Receiving
(ID = 03)
H'AA
(MPB = 0)
processor D
Receiving
(ID = 04)

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