HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 14

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

1.1
The SH7011 CMOS single-chip microprocessors integrate a Hitachi-original architecture, high-
speed CPU with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set Most instructions can be executed in one clock cycle,
which greatly improves instruction execution speed In addition, the 32-bit internal-bus
architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds.
In addition, the SH7011 includes on-chip peripheral functions necessary for system configuration,
such as large-capacity ROM, timers, a serial communication interface (SCI), an A/D converter, an
interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an
external memory access support function. This greatly reduces system cost.
1.1.1
CPU:
Original Hitachi architecture
32-bit internal data bus
General-register machine
RISC-type instruction set
Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation)
Address space: Architecture supports 4 Gbytes
On-chip multiplier: multiplication operations (32 bits 32 bits
multiplication/accumulation operations (32 bits
to four cycles
Five-stage pipeline
Sixteen 32-bit general registers
Three 32-bit control registers
Four 32-bit system registers
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture (basic operations are executed between registers)
Delayed branch instructions reduce pipeline disruption during branch
Instruction set based on C language
SH7011 Overview
SH7011 Features
Section 1 SH7011 Overview
32 bits + 64 bits
64 bits) and
64 bits) executed in two
1