HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 11

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.3 Operation ........................................................................................................................... 176
10.4 Interrupts............................................................................................................................ 177
Section 11 Compare Match Timer (CMT)
11.1 Overview............................................................................................................................ 179
11.2 Register Descriptions......................................................................................................... 182
11.3 Operation ........................................................................................................................... 185
11.4 Interrupts............................................................................................................................ 186
11.5 Notes on Use...................................................................................................................... 188
Section 12 Serial Communication Interface (SCI)
12.1 Overview............................................................................................................................ 191
12.2 Register Descriptions......................................................................................................... 193
10.2.3 Timer 2 Constant Register (T2COR) ................................................................... 175
10.3.1 Cyclic Count Operation........................................................................................ 176
10.3.2 T2CNT Count Timing.......................................................................................... 176
10.4.1 Interrupt Source.................................................................................................... 177
10.4.2 Timing of Compare Match Flag Setting .............................................................. 177
10.4.3 Timing of Compare Match Flag Clearing ............................................................ 178
11.1.1 Features ................................................................................................................ 179
11.1.2 Block Diagram...................................................................................................... 180
11.1.3 Register Configuration ......................................................................................... 181
11.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 182
11.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 183
11.2.3 Compare Match Timer Counter (CMCNT).......................................................... 184
11.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 185
11.3.1 Period Count Operation........................................................................................ 185
11.3.2 CMCNT Count Timing ........................................................................................ 186
11.4.1 Interrupt Sources .................................................................................................. 186
11.4.2 Compare Match Flag Set Timing ......................................................................... 186
11.4.3 Compare Match Flag Clear Timing...................................................................... 187
11.5.1 Contention between CMCNT Write and Compare Match ................................... 188
11.5.2 Contention between CMCNT Word Write and Incrementation .......................... 189
11.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 190
12.1.1 Features ................................................................................................................ 191
12.1.2 Block Diagram...................................................................................................... 192
12.1.3 Pin Configuration ................................................................................................. 192
12.1.4 Register Configuration ......................................................................................... 193
12.2.1 Receive Shift Register (RSR)............................................................................... 193
12.2.2 Receive Data Register (RDR) .............................................................................. 194
12.2.3 Transmit Shift Register (TSR).............................................................................. 194
12.2.4 Transmit Data Register (TDR) ............................................................................ 194
12.2.5 Serial Mode Register (SMR)................................................................................ 195
................................................................... 179
.................................................... 191
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