HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 244

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.1.4
Table 13.2 shows the configuration of the A/D converter registers.
Table 13.2 Register Configuration
Name
A/D data register AH
A/D data register AL
A/D data register BH
A/D data register BL
A/D data register CH
A/D data register CL
A/D data register DH
A/D data register DL
A/D control/status register ADCSR
A/D control register
Note: Only 0 can be written to bit 7 to clear the flag.
13.2
13.2.1
The A/D data registers (ADDR) are 16-bit read-only registers for storing A/D conversion results.
There are four of these registers, ADDRA through ADDRD.
The A/D-converted data is 10-bit data which is transferred to the ADDR for the selected channel
for storage. The upper 8 bits of the converted data correspond to the upper byte of the ADDR, and
the lower 2 bits correspond to the lower byte. Bits 5–0 of the lower byte of the ADDR are
reserved, and always read 0. Table 13.3 shows the correspondence between the analog input
channels and the ADDR registers.
The ADDR registers can be read by the CPU at all times. The upper byte is read directly, but the
lower byte data is transferred via a temporary register (TEMP). For details, see section 13.3, CPU
Interface.
The ADDR registers are initialized to H'0000 by a power-on reset.
234
Register Configuration
Register Descriptions
A/D Data Registers A–D (ADDRA–ADDRD)
Abbreviation R/W
ADDRAH
ADDRAL
ADDRBH
ADDRBL
ADDRCH
ADDRCL
ADDRDH
ADDRDL
ADCR
R
R
R
R
R
R
R
R
R/(W)* H'00
R/W
Initial Value
H’00
H’00
H’00
H’00
H’00
H’00
H’00
H’00
H'7F
Address
H'FFFF8420
H'FFFF8421
H'FFFF8422
H'FFFF8423
H'FFFF8424
H'FFFF8425
H'FFFF8426
H'FFFF8427
H'FFFF8428
H'FFFF8429
Access Size
8,16
16
8,16
16
8,16
16
8,16
16
8,16
8,16