HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 118

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.4
The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel.
The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a power-
on reset.
Channel 0: TIER0
Channels 1, 2: TIER1, TIER2
Bit 7: TTGE
0
1
Bit 4: TCIEV
0
1
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an
A/D conversion start request by a TGRA register input capture/compare-match.
Bit 6—Reserved: This bit is reserved. It always reads as 1, and cannot be modified.
Bit 5—Reserved. This bit always reads 0. The write value should always be 0.
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the
overflow flag TCFV of the timer status register (TSR) is set to 1.
Initial value:
Initial value:
Timer Interrupt Enable Register (TIER)
R/W:
R/W:
Bit:
Bit:
TTGE
TTGE
R/W
R/W
7
0
7
0
Description
Disable A/D conversion start requests generation (initial value)
Enable A/D conversion start request generation
Description
Disable TCFV interrupt requests (TCIV) (initial value)
Enable TCFV interrupt requests (TCIV)
—
—
6
1
R
6
1
R
—
—
5
0
R
5
0
R
TCIEV
TCIEV
R/W
R/W
4
0
4
0
TGIED
R/W
—
3
0
3
0
R
TGIEC
R/W
—
2
0
2
0
R
TGIEB
TGIEB
R/W
R/W
1
0
1
0
TGIEA
TGIEA
R/W
R/W
0
0
0
0
107