HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 163

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.8.4
Note: An asterisk in this section represents the channel number.
Pin initialization procedures are described below for the numbered combinations in table 8.9. The
active level is assumed to be low.
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When making a transition to a mode (Normal, PWM1, PWM2) in which the pin output level is
selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR
setting.
In PWM mode 1, since a waveform is not output to the TIOC*B pin, setting TIOR will not
initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM
mode 1.
In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will
not initialize the pins. If initialization is required, carry it out in normal mode, then switch to
PWM mode 2.
In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting
TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode,
carry out initialization, then set buffer mode again.
In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not
initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization,
then set buffer mode again.
Overview of Initialization Procedures and Mode Transitions in Case of Error
During Operation, Etc.