HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 230

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into the RSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
Figure 12.7 shows an example of SCI receive operation in the asynchronous mode.
Table 12.7 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
220
internally and starts receiving.
checks:
a. Parity check. The number of 1s in the receive data must match the even or odd parity
b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR into the
If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the
RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 12.16.
Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF
bit is not set to 1, so be sure to clear the error flags.
SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also
set to 1, the SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in the SMR.
is checked.
RDR.
Abbreviation
ORER
FER
PER
Condition
Receiving of next data ends while
RDRF is still set to 1 in SSR
Stop bit is 0
Parity of receive data differs from
even/odd parity setting in SMR
Data Transfer
Receive data not loaded
from RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR