HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 75

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.3
6.3.1
Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in
table 6.4.
Table 6.4
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4 and 3–0. Interrupt
priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. 8-bit
timers 1 and 2 are set to the same priority rank.
64
Initial value:
Initial value:
Description of Registers
Interrupt Priority Registers A–H (IPRA–IPRH)
Interrupt Request Sources and IPRA–IPRH
R/W:
R/W:
Bit:
Bit:
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
15–12
IRQ0
IRQ4
Reserved
MTU0
MTU2
Reserved
A/D
TIM1, 2
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
11–8
IRQ1
IRQ5
Reserved
MTU0
MTTU2
Reserved
Reserved
Reserved
R/W
R/W
11
0
3
0
Bits
7–4
IRQ2
IRQ6
Reserved
MTU1
Reserved
Reserved
CMT0
Reserved
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
3–0
IRQ3
IRQ7
Reserved
MTU1
Reserved
SCI
CMT1
Reserved
R/W
R/W
8
0
0
0