HD6417011VX20V Renesas Electronics America, HD6417011VX20V Datasheet - Page 248

• Manufacturer Part Number: HD6417011VX20V
• Description: MPU 5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7010r

Specifications of HD6417011VX20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: POR, PWM
• Number Of I /o: 11
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 7: TRGE
0
1
13.3
ADDRA–ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, while the upper byte is accessed directly by the CPU, the lower byte is accessed via an
8-bit temporary register (TEMP).
Data is read from an ADDR register as follows. When the upper byte is read, the upper-byte value
is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when
the lower byte is read, the TEMP contents are transferred to the CPU.
When reading an ADDR register, always read the upper byte before the lower byte. This operation
can be performed by reading ADDR from the upper byte address using a word transfer instruction
(such as MOV.W). It is possible to read only the upper byte, but if only the lower byte is read,
incorrect data may be obtained.
Figure 13.2 shows the data flow for access to an ADDR register.
238
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by MTU
trigger input.
Bits 6–0—Reserved: These bits always read 1. The write value should always be 1.
CPU Interface
Description
Disables A/D conversion start by MTU trigger input (initial value)
A/D conversion is started by MTU trigger