R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 66

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Page 36 of 1372
Type
Bus
control
Symbol
DQMU*
DQML*
RAS2*
RAS3*
RAS4*
RAS5*
RAS*
CAS*
WE*
WAIT-A
WAIT-B
OE-A*
OE-B*
CKE-A*
CKE-B*
1
1
1
3
3
3
3
2
2
1
*
*
1
1
1
3
3
Pin No.
H8S/2426, H8S/2426R
PLQP0144KA-A PTLG0145JB-A
85
86
109
110
35
36
109
110
35
84
56
38
137
38
137
H12
H10
A12
A13
L1
M1
A12
A13
L1
J11
N7
M2
A5
M2
A5
H8S/2424
PLQP0120LA-A,
PLQP0120KA-A
⎯
⎯
91
92
⎯
⎯
⎯
⎯
⎯
69
47
69
113
⎯
⎯
I/O
Output
Output
Output
Output
Output
Output
Input
Output
Output
H8S/2426, H8S/2426R, H8S/2424 Group
Function
Upper data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM space. Also
functions as the data mask enable
signal for accessing the 8-bit
continuous synchronous DRAM
space.
Lower-data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM interface
space.
Row address strobe signal for the
DRAM when the DRAM interface is
set. Row address strobe signal
when areas 2 to 5 are set as the
continuous DRAM space.
Row address strobe signal for the
synchronous DRAM when the
synchronous DRAM interface is
set.
Column address strobe signal for
the synchronous DRAM when the
synchronous DRAM interface is
set.
Write enable signal for the
synchronous DRAM when the
synchronous DRAM interface is
set.
Requests insertion of a wait state
in the bus cycles when accessing
an external 3-state address space.
Output enable signal when
accessing the DRAM space.
Clock enable signal when the
synchronous DRAM interface is
set.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010