R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 179
R4F24269NVFQV
Manufacturer Part Number
R4F24269NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24269NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * Not supported by the H8S/2424 Group.
6.1
• Manages external address space in area units
• Basic bus interface
• Burst ROM interface
• Address/data multiplexed I/O interface
• DRAM interface*
• Synchronous DRAM interface*
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM*
be set
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait cycles can be inserted for each area
Extension cycles can be inserted while CS is asserted for each area
Wait cycles can be inserted by the WAIT pin
The negation timing of the read strobe signal (RD) can be modified
Burst ROM interface can be set independently for areas 0 and 1
Address/data multiplexed I/O interface can be set for areas 6 and 7
DRAM interface can be set for areas 2 to 5
Continuous synchronous DRAM space can be set for areas 2 to 5
Features
1
Section 6 Bus Controller (BSC)
1
, synchronous DRAM*
2
2
, and address/data multiplexed I/O interfaces can
Section 6 Bus Controller (BSC)
Page 149 of 1372
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