R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 295

MCU 256KB FLASH 64K 144-LQFP

R4F24269NVFQV

Manufacturer Part Number
R4F24269NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24269NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2426, H8S/2426R, H8S/2424 Group
Section 6 Bus Controller (BSC)
6.8.12
Burst Operation
With synchronous DRAM, in addition to full access (normal access) in which data is accessed by
outputting a row address for each access, burst access is also provided which can be used when
making consecutive accesses to the same row address. This access enables fast access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal
cannot be specified to the Tc2 cycle data output if the Tc1 cycle is executed for second or
following column address when the CAS latency is set to 1 to issue the READ command. Do not
set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected.
(1)
Burst Access Operation Timing
Figure 6.64 shows the operation timing for burst access. When there are consecutive access cycles
for continuous synchronous DRAM space, the column address output cycles continue as long as
the row address is the same for consecutive access cycles. The row address used for the
comparison is set with bits MXC2 to MXC0 in DRAMCR.
REJ09B0466-0350 Rev. 3.50
Page 265 of 1372
Jul 09, 2010

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