R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 193

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
6.3.4
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
Read Strobe Timing Control Register (RDNCR)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an area
for which the RDNn bit is set to 1 is negated one
half-state earlier than that for an area for which the
RDNn bit is cleared to 0. The read data setup and
hold time specifications are also one half-state
earlier.
0: In an area n read access, the RD is negated at
1: In an area n read access, the RD is negated
the end of the read cycle
one half-state before the end of the read cycle
Section 6 Bus Controller (BSC)
Page 163 of 1372
(n = 7 to 0)