R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 15

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC) ......................................................407
8.1
8.2
8.3
8.4
8.5
8.6
Section 9 Data Transfer Controller (DTC) ........................................................475
9.1
9.2
9.3
Features.............................................................................................................................. 407
Input/Output Pins............................................................................................................... 409
Register Descriptions ......................................................................................................... 410
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Operation ........................................................................................................................... 422
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 449
8.4.11 Examples of Operation Timing in Each Mode ..................................................... 454
8.4.12 Ending DMA Transfer .......................................................................................... 468
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 469
Interrupt Sources................................................................................................................ 470
Usage Notes ....................................................................................................................... 472
Features.............................................................................................................................. 475
Register Descriptions ......................................................................................................... 477
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
Activation Sources............................................................................................................. 483
EXDMA Source Address Register (EDSAR)....................................................... 410
EXDMA Destination Address Register (EDDAR)............................................... 411
EXDMA Transfer Count Register (EDTCR)........................................................ 411
EXDMA Mode Control Register (EDMDR) ........................................................ 413
EXDMA Address Control Register (EDACR) ..................................................... 418
Transfer Modes..................................................................................................... 422
Address Modes ..................................................................................................... 423
DMA Transfer Requests ....................................................................................... 427
Bus Modes ............................................................................................................ 428
Transfer Modes..................................................................................................... 430
Repeat Area Function ........................................................................................... 432
Registers during DMA Transfer Operation .......................................................... 435
Channel Priority Order.......................................................................................... 439
EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 442
DTC Mode Register A (MRA) ............................................................................. 477
DTC Mode Register B (MRB).............................................................................. 479
DTC Source Address Register (SAR)................................................................... 480
DTC Destination Address Register (DAR)........................................................... 480
DTC Transfer Count Register A (CRA) ............................................................... 480
DTC Transfer Count Register B (CRB)................................................................ 480
DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 481
DTC Vector Register (DTVECR)......................................................................... 481
DTC Control Register (DTCCR) .......................................................................... 482
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