AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 29

• Manufacturer Part Number: AT90CAN128-15AZ
• Description: MCU AVR 128K FLASH 15MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-15AZ

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 53
• Eeprom Size: 4K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: CAN, I²C, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5.3
4.5.4
4.5.5
7679H–CAN–08/08
Address Latch Requirements
Pull-up and Bus-keeper
Timing
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
tion 26.9 on page
when calculating the access time requirement of the external component. The data setup time
before G low (t
(dependent on the capacitive load).
Figure 4-5.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
AT90CAN32/64/128 XMEM interface provides four different wait-states as shown in
is important to consider the timing specification of the External Memory device before selecting
the wait-state. The most important parameters are the access time for the external memory
compared to the set-up requirement of the AT90CAN32/64/128. The access time for the Exter-
nal Memory is defined to be the time from receiving the chip select/address until the data of this
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the
External SRAM Connected to the AVR
SU
h
) must not exceed address valid to ALE low (t
= 5 ns. Refer to t
375. The D-to-Q propagation delay (t
AVR
AD7:0
A15:8
ALE
WR
PD
RD
).
SU
LAXX_LD
).
TH
/
).
t
LLAXX_ST
“External Memory Control Register B – XMCRB”
D
G
in
Q
Table 26-7
PD
AT90CAN32/64/128
) must be taken into consideration
AVLLC
through
) minus PCB wiring delay
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
Table 26-14
Table
of
4-4. It
Sec-
29