AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 158

• Manufacturer Part Number: AT90CAN128-15AZ
• Description: MCU AVR 128K FLASH 15MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-15AZ

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 53
• Eeprom Size: 4K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: CAN, I²C, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

158
AT90CAN32/64/128
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 14-1.
Note:
• Bit 5:4 – COM2A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM21:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 14-2.
Table 14-3
mode.
Table 14-3.
Note:
Mode
COM2A1
COM2A1
0
1
2
3
0
0
1
1
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
150.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
pare match is ignored, but the set or clear is done at TOP. See
for more details.
shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM2A0
COM2A0
0
1
0
1
0
1
0
1
Table 14-2
WGM20
(PWM2)
0
1
0
1
Description
Normal port operation, OC2A disconnected.
Reserved
Clear OC2A on compare match.
Set OC2A at TOP.
Set OC2A on compare match.
Clear OC2A at TOP.
Description
Normal port operation, OC2A disconnected.
Toggle OC2A on compare match.
Clear OC2A on compare match.
Set OC2A on compare match.
Timer/Counter
Mode of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
shows the COM2A1:0 bit functionality when the WGM21:0 bits
(1)
Table 14-1
(1)
TOP
0xFF
0xFF
OCR2A
0xFF
“Fast PWM Mode” on page 152
Update of
OCR2A at
Immediate
TOP
Immediate
TOP
and
“Modes of Operation”
7679H–CAN–08/08
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX