AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 174

• Manufacturer Part Number: AT90CAN128-15AZ
• Description: MCU AVR 128K FLASH 15MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-15AZ

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 53
• Eeprom Size: 4K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: CAN, I²C, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

174
AT90CAN32/64/128
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 16-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 16-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clk
the following table:
Table 16-4.
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
0
1
Figure 16-3
SPR1
0
0
1
1
0
0
1
1
and
Figure 16-4
Figure 16-3
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is sum-
and
Figure 16-4
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
IO
for an example. The CPOL
frequency f
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
clkio
7679H–CAN–08/08
is shown in