AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 112
![MCU AVR 128K FLASH 15MHZ 64TQFP](/photos/37/62/376245/tqfp-64_sml.jpg)
AT90CAN128-15AZ
Manufacturer Part Number
AT90CAN128-15AZ
Description
MCU AVR 128K FLASH 15MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-15AZ
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
53
Eeprom Size
4K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
CAN, I²C, SPI, UART/USART
Core Size
8-Bit
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
CAN, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
90C
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-15AZ
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
AT90CAN128-15AZ
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
AT90CAN128-15AZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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12.9.3
12.9.4
12.9.5
112
AT90CAN32/64/128
Output Compare Register A – OCR0A
Timer/Counter0 Interrupt Mask Register – TIMSK0
Timer/Counter0 Interrupt Flag Register – TIFR0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
• Bit 7..2 – Reserved Bits
These are reserved bits for future use.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt
Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at
0x00.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
R
7
0
7
–
0
7
–
0
R/W
R
R
6
0
6
–
0
6
–
0
R/W
R
R
5
0
5
–
0
5
–
0
R/W
R
0
R
4
OCR0A[7:0]
0
4
–
4
–
0
R/W
3
0
3
–
R
0
3
–
R
0
R/W
R
R
2
0
2
–
0
2
–
0
OCIE0A
OCF0A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE0
TOV0
R/W
R/W
R/W
0
0
0
0
0
0
TIMSK0
OCR0
TIFR0
7679H–CAN–08/08
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