AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 143

• Manufacturer Part Number: AT90CAN128-15AZ
• Description: MCU AVR 128K FLASH 15MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-15AZ

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 53
• Eeprom Size: 4K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: CAN, I²C, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.11.19 Timer/Counter1 Interrupt Flag Register – TIFR1
13.11.20 Timer/Counter3 Interrupt Flag Register – TIFR3
7679H–CAN–08/08
• Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 1 – OCIEnA: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Counter Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICFn: Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn flag is set when the
counter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 4 – Reserved Bit
This bit is reserved for future use.
• Bit 3 – OCFnC: Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
R
7
–
0
7
–
0
(See “Interrupts” on page
(See “Interrupts” on page
R
R
6
–
0
6
–
0
60.) is executed when the TOVn flag, located in TIFRn, is set.
ICF1
ICF3
R/W
R/W
5
0
5
0
4
–
R
0
4
–
R
0
60.) is executed when the OCFnB flag, located in
60.) is executed when the OCFnA flag, located in
OCF1C
OCF3C
R/W
R/W
3
0
3
0
OCF1B
OCF3B
R/W
R/W
2
0
2
0
AT90CAN32/64/128
OCF1A
OCF3A
R/W
R/W
1
0
1
0
TOV1
TOV3
R/W
R/W
0
0
0
0
TIFR1
TIFR3
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