AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 736

IC MCU ARM9 64K SRAM 144LFBGA

AT91SAM9R64-CU-999

Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9R64-CU-999

Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9R64-CU-999
Manufacturer:
Atmel
Quantity:
10 000
Table 41-2.
41.4.3
Table 41-3.
Notes:
41.4.4
736
Transfer
Control
Isochronous
Interrupt
Bulk
CONTROL
(bidirectional)
IN
(device toward host)
OUT
(host toward device)
1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
AT91SAM9R64/RL64 Preliminary
USB Transfer Event Definitions
USB V2.0 High Speed BUS Transactions
USB Communication Flow
USB Transfer Events
Control Transfers
Bulk IN Transfer
Interrupt IN Transfer
Isochronous IN Transfer
Bulk OUT Transfer
Interrupt OUT Transfer
Isochronous OUT Transfer
A transfer is composed of one or several transactions;
An endpoint handles all transactions related to the type of transfer for which it has been
configured.
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
Unidirectional
Unidirectional
Unidirectional
Bidirectional
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
Direction
(1)
(2)
(2)
Not guaranteed
Not guaranteed
Not guaranteed
Guaranteed
Bandwidth
• Setup transaction → Data IN transactions → Status OUT transaction
• Setup transaction → Data OUT transactions → Status IN transaction
• Setup transaction → Status IN transaction
• Data IN transaction → Data IN transaction
• Data IN transaction → Data IN transaction
• Data IN transaction → Data IN transaction
• Data OUT transaction → Data OUT transaction
• Data OUT transaction → Data OUT transaction
• Data OUT transaction → Data OUT transaction
Endpoint Size
8,16,32,64
8-1024
8-1024
8-512
Error Detection
Yes
Yes
Yes
Yes
6289C–ATARM–28-May-09
Automatic
Retrying
Yes
Yes
No

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