AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 609

• Manufacturer Part Number: AT91SAM9R64-CU-999
• Description: IC MCU ARM9 64K SRAM 144LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37.5.13
Name: DMAC_CTRLAx [x = 0..1]
Access: Read/Write
Reset Value: 0x00000000
• BTSIZE
Buffer Transfer Size. The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the
number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of
transfers completed on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when
the relevant channel is enabled.
• SRC_WIDTH
• DST_WIDTH
• DONE
0: The transfer is performed.
1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con-
tent of this register.
The DONE field is written back to memory at the end of the transfer.
6289C–ATARM–28-May-09
DONE
31
23
15
–
7
SRC_WIDTH
DST_WIDTH
DMAC Channel x [x = 0..1] Control A Register
00
01
1X
1X
00
01
30
22
14
–
–
6
Single Transfer Size
Single Transfer Size
HALF-WORD
HALF-WORD
WORD
BYTE
29
21
13
WORD
–
5
BYTE
DST_WIDTH
28
20
12
–
4
BTSIZE
BTSIZE
AT91SAM9R64/RL64 Preliminary
27
19
11
–
–
3
26
18
10
–
–
2
25
17
–
9
1
SRC_WIDTH
24
16
–
8
0
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