PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 48

• Manufacturer Part Number: PIC18F87K90-I/PTRSL
• Description: MCU PIC 128K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 4096Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87K90 FAMILY
3.6.2
The 4x Phase Locked Loop (PLL) can be used with the
HF-INTOSC to produce faster device clock speeds
than are normally possible with the internal oscillator
sources. When enabled, the PLL produces a clock
speed of 16 MHz or 64 MHz.
PLL operation is controlled through software. The con-
trol bits, PLLEN (OSCTUNE<6>) and PLLCFG
(CONFIG1H<4>), are used to enable or disable its
operation. The PLL is available only to HF-INTOSC
and the other oscillator is set with HS and EC modes.
Additionally, the PLL will only function when the
selected output frequency is either 4 MHz or 16 MHz
(OSCCON<6:4> = 111, 110 or 101).
Like the INTIO modes, there are two distinct INTPLL
modes available:
• In INTPLL1 mode, the OSC2 pin outputs F
• In INTPLL2 mode, OSC1 functions as RA7 and
3.6.3
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 16 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0>
register (Register 3-3).
When the OSCTUNE register is modified, the INTOSC
(HF-INTOSC and MF-INTOSC) frequency will begin
shifting to the new frequency. The oscillator will require
some time to stabilize. Code execution continues
during this shift and there is no indication that the shift
has occurred.
The LF-INTOSC oscillator operates independently of
the HF-INTOSC or the MF-INTOSC source. Any
changes in the HF-INTOSC or the MF-INTOSC source,
across voltage and temperature, are not necessarily
reflected by changes in LF-INTOSC or vice versa. The
frequency of LF-INTOSC is not affected by OSCTUNE.
3.6.4
The INTOSC frequency may drift as V
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. Depending on the device, this may have no
effect on the LF-INTOSC clock source frequency.
DS39957B-page 48
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (Figure 3-8).
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2
(Figure 3-9).
INTPLL MODES
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
INTOSC FREQUENCY DRIFT
(OSCTUNE<5:0>)
in
the
DD
or tempera-
OSCTUNE
OSC
/4,
Preliminary
compensation techniques are shown here.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
3.6.4.1
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.6.4.2
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the SOSC
oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
3.6.4.3
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
Compensating with the EUSART
Compensating with the Timers
Compensating with the CCP Module
in Capture Mode
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