PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 174

• Manufacturer Part Number: PIC18F87K90-I/PTRSL
• Description: MCU PIC 128K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 4096Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87K90 FAMILY
TABLE 11-14: PORTG FUNCTIONS (CONTINUED)
TABLE 11-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
DS39957B-page 174
PORTG
TRISG
LCDSE3
ANCON2
ODCON1
ODCON2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
RG2/RX2/DT2/
AN18/C3INA
RG3/CCP4/AN17/
P3D/C3INB
RG4/SEG26/
RTCC/T7CKI/
T5G/CCP5/
AN16/P1D/
C3INC
RG5
Legend:
Pin Name
Name
Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
SSP1OD
CCP10OD
SE31
Function
Bit 7
SEG26
C3INA
C3INB
C3INC
T7CKI
—
—
CCP4
RTCC
CCP5
AN18
AN17
AN16
RG2
RG3
RG4
RX2
DT2
P3D
T5G
P1D
CCP2OD CCP1OD
CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD
Setting
SE30
Bit 6
TRIS
—
—
0
1
1
1
1
1
x
0
1
0
1
1
x
0
0
1
1
x
x
x
0
1
1
x
0
I/O
O
O
O
O
O
O
O
O
O
O
RG5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SE29
Bit 5
—
(1)
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
Preliminary
TRISG4
SE28
Bit 4
RG4
—
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
A/D Input Channel 18. Default input configuration on POR. Does not
affect digital output.
Comparator 3 Input A.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare/PWM output. Takes priority over port data.
CCP4 capture input.
A/D Input Channel 17. Default input configuration on PR. Does not
affect digital output.
Comparator 3 Input B.
ECCP3 PWM Output D. May be configured for tri-state during
Enhanced PWM.
LATG<4> data output.
PORTG<4> data input.
LCD Segment 26 output; disables all other pin functions.
RTCC output.
Timer7 clock input.
Timer5 external clock gate input.
CCP5 compare/PWM output. Takes priority over port data.
CCP5 capture input.
A/D Input Channel 17. Default input configuration on POR. Does not
affect digital output.
Comparator 3 Input C.
ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
See the MCLR/RG5 pin.
TRISG3
SE27
Bit 3
RG3
—
TRISG2
SE26
Bit 2
RG2
—
Description
TRISG1
SE25
Bit 1
RG1
 2010 Microchip Technology Inc.
—
SSP2OD
TRISG0
SE24
Bit 0
RG0
Values on
Reset
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