PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 383

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PIC18F87K90-I/PTRSL

Manufacturer Part Number
PIC18F87K90-I/PTRSL
Description
MCU PIC 128K FLASH XLP 80TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
4096Byte
Cpu Speed
16MIPS
No. Of Timers
11
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Timers
11
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
A/d Bit Size
12 bit
A/d Channels Available
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
PIC18F87K90-I/PTRSL
Manufacturer:
Maxim
Quantity:
89
Part Number:
PIC18F87K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
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23.7
Figure 23-6 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 23-7 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits set to ‘ 010 ’ and a 4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
FIGURE 23-6:
FIGURE 23-7:
 2010 Microchip Technology Inc.
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
1
T
Set GO/DONE bit
conversion
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
T
- T
ACQT
Automatic
Acquisition
Time
2
AD
Conversion starts
Cycles
T
AD
3
1
sample.
A/D CONVERSION T
A/D CONVERSION T
T
b11
AD
AD
4
2
acquisition time selected.
Conversion starts
(Holding capacitor is disconnected)
T
AD
b10
1
3
This
T
b11
AD
b9
2
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
4
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
means
T
b10
AD
3
b8
AD
5
AD
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is reconnected to analog input.
T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
AD
the
b7
b9
4
6
T
AD
b6
5
b8
7
PIC18F87K90 FAMILY
T
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
T
AD
b7
AD
b5
6
Note:
AD
8
Cycles
wait is required before the next acquisition can be
T
b6
AD
7
b4
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
b5
AD
8
b3
10
T
b4
AD
9
b2
ACQ
ACQ
11
T
10
b3
= 0)
AD
= 4 T
b1
12
b2
T
AD
11
AD
b0
DS39957B-page 383
)
13
12
b1
13
b0

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