PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 369

• Manufacturer Part Number: PIC18F87K90-I/PTRSL
• Description: MCU PIC 128K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 4096Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
22.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 22-9:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTA1
TXREG1
TXSTA1
BAUDCON1 ABDOVF
SPBRGH1
SPBRG1
RCSTA2
TXREG2
TXSTA2
BAUDCON2 ABDOVF
SPBRGH2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSART1 Transmit Register
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART2 Transmit Register
EUSART2 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
TMR5GIF
TMR5GIE
TMR5GIP
CSRC
CSRC
SPEN
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
LCDIF
LCDIE
LCDIP
RCIDL
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
RX9
TX9
TX9
RXDTP
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
Preliminary
TXCKP
TXCKP
INT0IE
CREN
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SYNC
Bit 4
PIC18F87K90 FAMILY
CTMUIE
CTMUIP
CTMUIF
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
ADDEN
SENDB
BRG16
BRG16
e)
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR1GIF
TMR1GIE
TMR1GIP
TMR0IF
CCP2IF
CCP2IE
CCP2IP
BRGH
BRGH
FERR
FERR
Bit 2
—
—
TMR2IE
TMR2IP
TMR2IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
OERR
OERR
TRMT
TRMT
WUE
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
DS39957B-page 369
on Page:
Values
Reset
73
75
75
75
75
75
75
75
75
75
77
74
75
79
80
79
79
80
80