PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 169

• Manufacturer Part Number: PIC18F87K90-I/PTRSL
• Description: MCU PIC 128K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 4096Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 11-10: PORTE FUNCTIONS (CONTINUED)
TABLE 11-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
 2010 Microchip Technology Inc.
PORTE
LATE
TRISE
LCDCON
LCDSE3
ODCON1
ODCON2
PADCFG1
Legend: Shaded cells are not used by PORTE.
Note 1:
RE7/ECCP2/
P2A/SEG31
Legend:
Note 1:
Name
Pin Name
Not available on 64-pin devices.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD
SSP1OD
TRISE7
LCDEN
LATE7
RDPU
SE31
Bit 7
RE7
Function
ECCP2
SEG31
RE7
P2A
(1)
CCP2OD CCP1OD
TRISE6
SLPEN
LATE6
REPU
SE30
Bit 6
RE6
Setting
TRIS
0
1
0
1
0
1
RJPU
TRISE5
WERR
LATE5
SE29
Bit 5
RE5
I/O
O
O
O
O
I
I
(1)
Type
ANA
DIG
DIG
I/O
ST
ST
TRISE4
—
LATE4
SE28
Bit 4
RE4
Preliminary
—
—
—
LATE<7> data output.
PORTE<7> data input.
ECCP2 compare/PWM output; takes priority over port data.
ECCP2 capture input.
ECCP2 PWM Output A. May be configured for tri-state during
Enhanced PWM shutdown event.
Segment 31 analog output for LCD; disables digital output.
TRISE3
LATE3
SE27
PIC18F87K90 FAMILY
Bit 3
RE3
CS1
—
—
RTSECSEL1 RTSECSEL0
CCP5OD
TRISE2
LATE2
SE26
Bit 2
RE2
CS0
—
Description
CCP4OD
TRISE1
LMUX1
LATE1
SE25
Bit 1
RE1
—
CCP3OD
SSP2OD
TRISE0
LMUX0
LATE0
DS39957B-page 169
SE24
Bit 0
RE0
—
on Page:
Values
Reset
76
76
76
81
81
79
79
78