PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 284

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PIC18F87K90-I/PTRSL

Manufacturer Part Number
PIC18F87K90-I/PTRSL
Description
MCU PIC 128K FLASH XLP 80TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
4096Byte
Cpu Speed
16MIPS
No. Of Timers
11
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Timers
11
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
A/d Bit Size
12 bit
A/d Channels Available
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
PIC18F87K90-I/PTRSL
Manufacturer:
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Quantity:
89
Part Number:
PIC18F87K90-I/PTRSL
Manufacturer:
Microchip Technology
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PIC18F87K90 FAMILY
20.7
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
TABLE 20-5:
TABLE 20-6:
DS39957B-page 284
Multiplex
LP<3:0>
Note:
Static
1/2
1/3
1/4
1
2
3
4
5
6
7
LCD Frame Frequency
Clock
Timer1 Osc/32 or INTRC/32.
Clock Source/(4 x 1 x (LP<3:0> + 1))
Clock Source/(2 x 2 x (LP<3:0> + 1))
Clock Source/(1 x 3 x (LP<3:0> + 1))
Clock Source/(1 x 4 x (LP<3:0> + 1))
Static
125
83
62
50
42
36
31
FRAME FREQUENCY
FORMULAS
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
F
32.768 kHz OR INTRC OSC
OSC
source
Frame Frequency =
AT 32 MHz, TIMER1 AT
125
1/2
83
62
50
42
36
31
is
167
111
1/3
83
67
56
48
42
(F
OSC
/4)/8192,
125
1/4
83
62
50
42
36
31
Preliminary
component and can take only one of the two rms values.
20.8
LCD waveform generation is based on the philosophy
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC
The higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveforms:
Type-A and Type-B. In a Type-A waveform, the phase
changes within each common type, whereas a Type-B
waveform’s phase changes on each frame boundary.
Thus, Type-A waveforms maintain 0 V
frame, whereas Type-B waveforms take two frames.
Figure 20-7 through Figure 20-17 provide waveforms
for static, half-multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
Note 1: If Sleep has to be executed with LCD Sleep
2: When the LCD clock source is (F
LCD Waveform Generation
enabled
care must be taken to execute Sleep only
when V
8192, if Sleep is executed irrespective of
the LCDCON<SLPEN> setting, the LCD
goes into Sleep. Thus, take care to see
that V
executed.
DC
DC
on all pixels is ‘0’ when Sleep is
(SLPEN
on all the pixels is ‘0’.
 2010 Microchip Technology Inc.
(LCDCON<6>) = 1),
DC
over a single
OSC
/4)/

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