PIC18F87K90-I/PTRSL Microchip Technology, PIC18F87K90-I/PTRSL Datasheet - Page 340

• Manufacturer Part Number: PIC18F87K90-I/PTRSL
• Description: MCU PIC 128K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 4096Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87K90 FAMILY
21.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into an inactive state
(Figure 21-25).
21.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25:
FIGURE 21-26:
DS39957B-page 340
BRG
) and the SCLx pin is deasserted (pulled high).
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
Note: T
Sequence
Write to SSPxCON2,
SSPxIF
Note: T
SDAx
SCLx
Falling Edge of
9th Clock
BRG
Acknowledge Sequence Starts Here,
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
= one Baud Rate Generator period.
ACK
Set PEN
= one Baud Rate Generator period.
the End of Receive
Enable
ACKEN = 1, ACKDT = 0
SSPxIF Set at
Write to SSPxCON2,
BRG
T
T
bit,
BRG
; the SCLx pin
BRG
SDAx Asserted Low Before Rising Edge of Clock
to Set Up Stop Condition
8
D0
ACKEN
T
SCLx Brought High After T
BRG
Preliminary
P
Cleared in
T
Software
BRG
SCLx = 1 for T
After SDAx Sampled High. P bit (SSPxSTAT<4>) is Set.
T
BRG
ACK
21.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set (Figure 21-26).
21.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
of Acknowledge Sequence
SSPxIF Set at the End
PEN bit (SSPxCON2<2>) is Cleared by
T
BRG
Hardware and the SSPxIF bit is Set
9
BRG
BRG
, Followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN Automatically Cleared
(Baud Rate Generator rollover count)
 2010 Microchip Technology Inc.
Cleared in
Software
BRG
BRG
later, the PEN bit is