ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 351

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5
4921E–AUTO–09/09
DATA TRANSFER INSTRUCTIONS
Note:
Mnemonics
MOVW
MOV
SPM
SES
SEV
SEH
CLH
LDD
LDD
STD
STD
LPM
LPM
LPM
OUT
CLS
SET
LDS
STS
CLV
CLT
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Instruction Set Summary (Continued)
1. These instructions are only available in ATA6603
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
X+, Rr
- X, Rr
Y+, Rr
Rd, -Z
- Y, Rr
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, k
X, Rr
Y, Rr
Z, Rr
k, Rr
P, Rr
Description
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Move Between Registers
Copy Register Word
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect with Displacement
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
Store Indirect and Pre-Dec.
Store Direct to SRAM
Out Port
Operation
I
S
S
V
V
T
T
H
H
Rd
Rd+1:Rd
Rd
Rd
Rd
X
Rd
Rd
Y
Rd
Rd
Rd
Z
Rd
Rd
(X)
(X)
X
(Y)
(Y)
Y
(Y + q)
(Z)
(Z)
Z
(Z + q)
(k)
R0
Rd
Rd
(Z)
Rd
P
0
1
0
Z - 1, Rd
Z - 1, (Z)
1
0
1
0
X - 1, Rd
Y - 1, Rd
X - 1, (X)
Y - 1, (Y)
Rr
1
0
Rr
Rr
(X)
(X), X
(Y)
(Y), Y
(Y + q)
(Z)
(Z), Z
(Z + q)
Rr
Rr, Z
(Z)
(Z)
(Z), Z
R1:R0
P
Rr
Rr, Y
Rr
Rr, X
K
(k)
Rr
Rr
Rr+1:Rr
Z + 1
Y + 1
X + 1
Z+1
Z+1
X + 1
Y + 1
(Z)
Rr
(X)
(Y)
Rr
Rr
ATA6602/ATA6603
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
S
S
V
V
T
T
H
H
I
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
-
351