ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 129

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.13
4.13.1
4.13.2
4.13.3
4921E–AUTO–09/09
Timer/Counter0 and Timer/Counter1 Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
on page 130
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
CLK_I/O
clk
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
I/O
T1
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is
executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to
125
). The latch is transparent in the high period of the internal system clock.
/clk
/1024.
and
T0
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
“Waveform Generation Mode Bit Description” on page
shows a functional equivalent block diagram of the T1/T0 synchronization and
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
T1
/clk
T
0
pulse for each positive (CSn2:0 = 7) or negative
ATA6602/ATA6603
CLK_I/O
/8, f
125.
CLK_I/O
Table 4-50 on page
/64, f
CLK_I/O
Figure 4-38
/256, or
129