ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 225

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.6.3
4921E–AUTO–09/09
USART MSPIM Control and Status Register n B - UCSRnB
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
• Bit 4 - RXENn: Receiver Enable
• Bit 3 - TXENn: Transmitter Enable
• Bit 2:0 - Reserved Bits in MSPI mode
Initial Value
Read/Write
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is
written to one and the UDREn bit in UCSRnA is set.
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will over-
ride normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush
the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and
TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and
since only master mode is supported.
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing
TXENn to zero) will not become effective until ongoing and pending transmissions are com-
pleted, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnB is written.
Bit
RXCIEn
R/W
7
0
TXCIEn
R/W
6
0
UDRIE
R/W
5
0
RXENn
R/W
4
0
TXENn
R/W
3
0
ATA6602/ATA6603
R
2
1
-
R
1
1
-
R
0
0
-
UCSRnB
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