ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 226

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.6.4
226
ATA6602/ATA6603
USART MSPIM Control and Status Register n C - UCSRnC
Table 4-85.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation (see
UMSELn1
0
0
1
1
• Bit 7:6 - UMSELn1:0: USART Mode Select
• Bit 5:3 - Reserved Bits in MSPI mode
• Bit 2 - UDORDn: Data Order
• Bit 1 - UCPHAn: Clock Phase
• Bit 0 - UCPOLn: Clock Polarity
Read/Write
Initial Value
These bits select the mode of operation of the USART as shown in
Control and Status Register n C – UCSRnC” on page 213
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM
is enabled.
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnC is written.
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of
the data word is transmitted first. Refer to the section
details.
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing
(last) edge of XCKn. Refer to the section
details.
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the section
Modes and Timing” on page 219
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
Bit
UMSELn1
UMSELn Bits Settings
R/W
7
0
“USART Baud Rate Registers – UBRRnL and UBRRnH” on page
1
0
1
UMSELn0
0
UMSELn0
R/W
6
0
for details.
R
5
0
-
R
4
0
-
“SPI Data Modes and Timing” on page 219
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
R
3
0
-
UDORDn
R/W
2
1
“Frame Formats” on page 196
for full description of the normal
UCPHAn
R/W
1
1
Table
4-85. See
UCPOLn
R/W
0
0
4921E–AUTO–09/09
“SPI Data
UCSRnC
“USART
215).
for
for