ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 279
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6603P-PLQW
Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6603P-PLQW.pdf
(360 pages)
Specifications of ATA6603P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 279 of 360
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4.21.6.4
4.21.6.5
4921E–AUTO–09/09
ADC Control and Status Register B – ADCSRB
Digital Input Disable Register 0 – DIDR0
Table 4-101. ADC Auto Trigger Source Selections
• Bit 7, 5:3 – Res: Reserved Bits
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
• Bits 7:6 – Res: Reserved Bits
• Bit 5..0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable
Read/Write
Initial Value
Initial Value
Read/Write
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trig-
ger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A
conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion.
Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set.
When an analog signal is applied to the ADC5..0 pin and the digital input from this pin is not
needed, this bit should be written logic one to reduce power consumption in the digital input
buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not
require Digital Input Disable bits.
Bit
Bit
ADTS2
0
0
0
0
1
1
1
1
R
R
7
–
0
7
–
0
ACME
ADTS1
R/W
R
6
–
0
6
0
0
0
1
1
0
0
1
1
.
ADC5D
R/W
R
5
0
5
–
0
ADC4D
R/W
ADTS0
R
4
0
4
–
0
0
1
0
1
0
1
0
1
ADC3D
R/W
R
3
–
0
3
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADC2D
ATA6602/ATA6603
ADTS2
R/W
R/W
2
0
2
0
ADC1D
ADTS1
R/W
R/W
1
0
1
0
ADC0D
ADTS0
R/W
R/W
0
0
0
0
ADCSRB
DIDR0
279
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