ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 267

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4-103. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 4-104. ADC Timing Diagram, Single Conversion
4921E–AUTO–09/09
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times (see
268).
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
12
3
13
Sample & Hold
4
14
5
15
Sample & Hold
16
6
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
21
Complete
22
Conversion
11
Complete
23
12
24
13
ATA6602/ATA6603
25
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
2
2
MUX and REFS
Update
MUX and REFS
Update
Table 4-97 on page
3
3
267