ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 246

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-90.
246
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x18
0x20
0x28
0x30
0x38
ATA6602/ATA6603
Status of the 2-wire Serial
Bus and 2-wire Serial
Interface Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted;
ACK has been received
SLA+W has been
transmitted;
NOT ACK has been
received
Data byte has been
transmitted;
ACK has been received
Data byte has been
transmitted;
NOT ACK has been
received
Arbitration lost in SLA+W or
data bytes
Status codes for Master Transmitter Mode
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-
out losing control of the bus.
TWCR
value
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action or
Load data byte or
Load data byte or
No TWDR action
No TWDR action
Load SLA+W or
To/from TWDR
TWINT
Load SLA+W
Load SLA+R
1
Application Software Response
TWEA
X
0
1
0
1
0
1
0
1
0
1
STA
0
0
0
0
1
0
1
0
1
0
1
TWSTA
0
0
1
1
0
0
1
1
0
0
STO
1
0
0
0
0
0
1
1
0
0
1
1
To TWCR
1
1
1
1
1
1
1
1
1
1
TWINT TWEA
1
1
1
1
1
1
1
1
1
1
1
TWSTO
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TWWC
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition
will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition
will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition
will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition
will be transmitted and TWSTO Flag will be reset
2-wire Serial Bus will be released and not
addressed Slave mode entered
A START condition will be transmitted when the
bus becomes free
X
TWEN
1
–
0
4921E–AUTO–09/09
TWIE
X