ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 288

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

288
ATA6602/ATA6603
• Bit 3 – BLBSET: Boot Lock Bit Set
• Bit 2 – PGWRT: Page Write
• Bit 1 – PGERS: Page Erase
• Bit 0 – SELFPRGEN: Self Programming Enable
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The
data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically
be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within
four clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the
SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the
Z-pointer) into the destination register. See
on page 292
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles executes Page Write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z-pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM
instruction is executed within four clock cycles. The CPU is halted during the entire Page
Write operation if the NRWW section is addressed.
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within
four clock cycles executes Page Erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-
tion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU
is halted during the entire Page Write operation if the NRWW section is addressed.
This bit enables the SPM instruction for the next four clock cycles. If written to one together
with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have
a special meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon
completion of an SPM instruction, or if no SPM instruction is executed within four clock
cycles. During Page Erase and Page Write, the SELFPRGEN bit remains high until the
operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the
lower five bits will have no effect.
for details.
“Reading the Fuse and Lock Bits from Software”
4921E–AUTO–09/09